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AT86RF232
If TRX_STATUS = 0x1F
(STATE_TRANSITION_IN_PROGRESS) the
Atmel
AT86RF232 is within a state transition. Do not try to initiate a further state change while
the radio transceiver is in STATE_TRANSITION_IN_PROGRESS.
Pin 11 (SLP_TR) is a multifunctional pin, refer to Section 6.5 . Depending on the radio
transceiver state, a rising edge of pin 11 (SLP_TR) causes the following state
transitions:
? TRX_OFF
? PLL_ON
?
?
SLEEP
BUSY_TX
(level sensitive)
Whereas the falling edge of pin SLP_TR causes the following state transitions:
? SLEEP
?
TRX_OFF
(level sensitive)
A low level on pin 8 (/RST) causes a reset of all registers (register bits CLKM_CTRL are
shadowed, for details refer to Section 9.6.4 ) and forces the radio transceiver into
TRX_OFF state. However, if the device was in P_ON state it remains in the P_ON
state.
For all states except SLEEP, the state change commands FORCE_TRX_OFF or
TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active
receive or transmit states (BUSY_*), the command FORCE_TRX_OFF interrupts these
active processes, and forces an immediate transition to TRX_OFF. In contrast a
TRX_OFF command is stored until an active state (receiving or transmitting) has been
finished. After that the transition to TRX_OFF is performed.
For a fast transition from any non sleep states to PLL_ON state, the command
FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF this command does not
disable PLL and analog voltage regulator (AVREG). It is not available in states P_ON,
SLEEP, or RESET.
The completion of each requested state change shall always be confirmed by reading
the register bits TRX_STATUS (register 0x01, TRX_STATUS).
Note:
1.
If FORCE_TRX_OFF and FORCE_PLL_ON commands are used, it is
recommended to set pin 11 (SLP_TR) = L before.
7.1.2 Basic Operating Mode Description
7.1.2.1 P_ON – Power-On after V DD
When the external supply voltage (V DD ) is firstly applied to the AT86RF232, the radio
transceiver goes into the P_ON state performing an on-chip reset. The crystal oscillator
is activated and the default 1MHz master clock is provided at pin 17 (CLKM) after the
crystal oscillator has stabilized. CLKM can be used as a clock source to the
microcontroller. The SPI interface and digital voltage regulator (DVREG) are enabled.
The on-chip power-on-reset sets all registers to their default values. A dedicated reset
signal from the microcontroller at pin 8 (/RST) is not necessary, but recommended for
hardware / software synchronization reasons.
All digital inputs are pulled-up or pulled-down during P_ON state, refer to Section 1.3.2 .
This is necessary to support microcontrollers where GPIO signals are floating after
power-on or reset. The input pull-up and pull-down circuitry is disabled when the radio
transceiver leaves the P_ON state. Output pins DIG1/DIG2 are pulled-down to digital
ground, unless their configuration is changed.
31
8321A – MCU Wireless – 10/11
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